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Modeling pFET currents after soft breakdown at different gate locations

dc.contributor.authorKaczer, Ben
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorDegraeve, Robin
dc.contributor.authorCrupi, Felice
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-15T14:05:50Z
dc.date.available2021-10-15T14:05:50Z
dc.date.issued2004-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9106
dc.sourceIIOimport
dc.titleModeling pFET currents after soft breakdown at different gate locations
dc.typeJournal article
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.source.peerreviewno
dc.source.beginpage125
dc.source.endpage129
dc.source.journalMicroelectronic Engineering
dc.source.issue1_4
dc.source.volume72
imec.availabilityPublished - imec


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