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Power estimation methods for sequential logic circuits

dc.contributor.authorTsui, Chi-Ying
dc.contributor.authorMonteiro, J.
dc.contributor.authorPedram, M.
dc.contributor.authorDevadas, S.
dc.contributor.authorDespain, A. M.
dc.contributor.authorLin, Bill
dc.date.accessioned2021-09-29T13:18:09Z
dc.date.available2021-09-29T13:18:09Z
dc.date.issued1995
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/921
dc.sourceIIOimport
dc.titlePower estimation methods for sequential logic circuits
dc.typeJournal article
dc.source.peerreviewno
dc.source.beginpage404
dc.source.endpage416
dc.source.journalIEEE Trans. Very Large Scale Integration (VLSI) Systems
dc.source.volume3
imec.availabilityPublished - imec


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