Show simple item record

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits

dc.contributor.authorVassilev, Vesselin
dc.contributor.authorVaschenko, Vladislav
dc.contributor.authorJansen, Philippe
dc.contributor.authorChoi, B.-J.
dc.contributor.authorConcannon, An
dc.contributor.authorYang, J.-J,
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorMahadeva Iyer, Natarajan
dc.contributor.authorTerbeek, Marcel
dc.contributor.authorHopper, Peter
dc.contributor.authorSteyaert, Michiel
dc.contributor.authorMaes, Herman
dc.date.accessioned2021-10-15T17:30:49Z
dc.date.available2021-10-15T17:30:49Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9843
dc.sourceIIOimport
dc.titleA CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
dc.typeJournal article
dc.contributor.imecauthorGroeseneken, Guido
dc.source.peerreviewno
dc.source.beginpage1885
dc.source.endpage1890
dc.source.journalMicroelectronics Reliability
dc.source.issue9_11
dc.source.volume44
imec.availabilityPublished - imec
imec.internalnotesSpecial issue 15th ESREF Symposium


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record