Browsing by Author "Ayala, Jose"
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Publication Design space exploration of distributed loop buffer architectures with incompatible loop-nest organisation in embedded systems
Journal article2013, Journal of Signal Processing Systems, 72, p.69-85Publication Energy impact in the design space exploration of loop buffer schemes in embedded systems
Proceedings paper2013, IFIP International Conference on VLSI - VLSI-SoC, 6/10/2013, p.216-221Publication Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures
Journal article2008-01, Integration, the VLSI Journal, (21) 1, p.38-48Publication Reduction of register file delay due to process variability in VLIW embedded processors
Proceedings paper2007-05, IEEE International Symposium on Circuits and Systems - ISCAS, 27/05/2007, p.121-124Publication Survey of low-energy techniques for instruction memory organisations in embedded systems
Journal article2013, Journal of Signal Processing Systems, (70) 1, p.1-19