Browsing by Author "Barat, F."
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Publication Clustered LO buffer organisation for low energy embedded processors
Proceedings paper2002, Proceedings 2nd Wsh.on Application-Specific (WASP) in conjunction with IEEE/ACM Int. Symp. on Microarchitecture - MICRO 35, 1/11/2002, p.54-61Publication Clustered loop buffer organization for low energy VLIW embedded processors
Journal article2005-06, IEEE Trans. on Computers, (54) 6, p.672-683Publication Instruction buffering exploration for low energy embedded processors
Proceedings paper2003, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Proc. 13th Int. Workshop, 10/09/2003, p.409-419Publication Instruction buffering exploration for low energy embedded processors
Journal article2005, Journal of Embedded Computing (JEC), (1) 3, p.341-351Publication L0 buffer energy optimisation through scheduling and exploration
Proceedings paper2004-03, Proceedings of the ACM Symposium on Applied Computing, p.905-906Publication L0 cluster synthesis and operation shuffling
Proceedings paper2004-09, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - PATMOS, 15/09/2004, p.311-321Publication Low energy clustered instruction fetch and split loop cache architecture for long instruction word processors
Proceedings paper2001, Proceedings of the Workshop on Compilers and Operating Systems for Low Power - COLP; Held in conjunction with: International Con, p.14.1-8Publication Low power coarse-grained reconfigurable instruction set processor
Proceedings paper2003, Field-Programmable Logic and Applications, 1/09/2003, p.230-239Publication Methodology for building processor design space exploration
Proceedings paper2005, Digest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3, 20/03/2005Publication Reconfigurable instruction set processors from a hardware/software perspective
Journal article2002, IEEE Trans. Software Engineering, (28) 9, p.847-862Publication Software transformations to reduce instruction memory power consumption using a loop buffer
; ; ; Deconinck, GeertProceedings paper2003, Int. Workshop on Optimisation for DSP and Embedded Systems (ODES) in conj. with Intnl. Symp on Code Generation and Optimization, 23/03/2003