Browsing by Author "Barat, Francisco"
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Publication A high-level memory energy estimator based on reuse distance
Proceedings paper2005-03, Digest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3, 19/03/2005Publication A low energy clustered instruction memory hierarchy for long instruction word processors
Proceedings paper2002, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS, 11/09/2002, p.258-267Publication A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V
Proceedings paper2011, IEEE International Solid-State Circuits Conference - ISSCC, 20/02/2011, p.332Publication Cluster generation and scheduling for instruction (L0) clusters
Proceedings paper2003, Program Acceleration through Application and Architecture driven Code Transformations - PA3CT, 22/09/2003, p.37-39Publication Design style case study for computer nodes of a heterogeneous NoC platform
Proceedings paper2004-12, 25th IEEE International Real-Time Systems Symposium, 5/12/2004, p.104-113Publication Instruction buffering exploration for low energy VLIWs with instruction clusters
Proceedings paper2004, Proceedings of the Asia and South Pacific Design Automation Conference - ASP-DAC, 27/01/2004, p.825-830Publication Low power coarse-grained reconfigurable instruction set processor
Proceedings paper2003, Program Acceleration through Application and Architecture driven Code Transformations - PA3CT, 22/09/2003, p.29-31