Browsing by Author "Cosemans, Stefan"
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Publication 8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes
Proceedings paper2011, 37th European solid-State Circuits Conference - ESSCIRC, 12/09/2011, p.531-534Publication A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in -Memory Analog Matrix -Vector-Multiplier for DNN Acceleration
Proceedings paper2021, IEEE Custom Integrated Circuits Conference (CICC), APR 25-30, 2021Publication A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W
Proceedings paper2023, IEEE 49th European Solid-State Circuits Conference (ESSCIRC), SEP 11-14, 2023, p.417-420Publication A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy
Journal article2011, IEEE Journal of Solid-State Circuits, (46) 10, p.2416-2430Publication A 4.4pJ/access 80MHz, 2K word x 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications
Proceedings paper2010, 36th European Solid-State Circuits Conference - ESSCIRC, 14/09/2010, p.358-361Publication A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
Journal article2012, IEEE Journal of Solid-State Circuits, (47) 7, p.1784-1796Publication A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
Proceedings paper2011, 37th European Solid-State Circuits Conference - ESSCIRC, 12/09/2011, p.519-522Publication A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
; ; ; ; ; Journal article2021, IEEE TRANSACTIONS ON ELECTRON DEVICES, (68) 8, p.3819-3825Publication A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh
Proceedings paper2011, 37th European Solid-State Circuits Conference - ESSCIRC, 12/09/2011, p.523-526Publication Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators
Journal article2022, IEEE DESIGN & TEST, (39) 2, p.48-55Publication Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write
Proceedings paper2012, 42nd European Solid-State Device Research Conference - ESSDERC, 17/09/2012, p.282-285Publication Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design
Proceedings paper2013, 5th IEEE International Memory Workshop - IMW, 26/05/2013, p.155-158Publication Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications
Proceedings paper2018, 48th European Solid-State Device Research Conference - ESSDERC, 3/09/2018, p.62-65Publication Benchmarking on-chip optical against electrical interconnect for high-performance applications
Proceedings paper2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 9/05/2011, p.3.2Publication Cell variability impact on the one-selector one-resistor cross-point array performance
Journal article2015, IEEE Transactions on Electron Devices, (62) 11, p.3490-3497Publication Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing
Proceedings paper2021, 19th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 13-16, 2021Publication Comparative analysis of RD and atomistic trap-based BTI models on SRAM sense amplifier
Proceedings paper2015, 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era - DTIS, 1/03/2015, p.1-6Publication Comparative BTI analysis for various sense amplifier designs
Proceedings paper2016, IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - DDECS, 20/04/2016, p.1-6Publication Comparative BTI impact for SRAM cell and sense amplifier designs
Proceedings paper2015, MEDIAN Finale - Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, 10/11/2015