Browsing by Author "Deconinck, G."
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Publication A low energy clustered instruction memory hierarchy for long instruction word processors
Proceedings paper2002, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS, 11/09/2002, p.258-267Publication A QoS framework for interactive 3D applications
Proceedings paper2002, 10th International Conference on Computer Graphics and Visualization, 4/02/2002, p.317-324Publication Automated dynamic memory data type implementation exploration and optimization
Publication Background data organisation exploration for the low-power implementation in real-time of a digital audio broadcast receiver on a SIMD processor
Proceedings paper2003, Design, Automation and Test in Europe Conference and Exhibition - DATE, 3/03/2003, p.1144-1145Publication Clustered loop buffer organization for low energy VLIW embedded processors
Journal article2005-06, IEEE Trans. on Computers, (54) 6, p.672-683Publication Data reuse exploration techniques for loop-dominated applications
Proceedings paper2002, DATE 02. Design Automation and Test in Europe Conference and Exhibition. Proceedings, 4/03/2002, p.428-435Publication Efficient data type identification in image processing applications with dynamic memory behaviour
Publication Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices
Proceedings paper2004, International Conference on Multimedia and Expo - ICME, 27/06/2004, p.60-63Publication Fast system-level prototyping of power-aware dynamic memory managers for embedded systems
Proceedings paper2003, Workshop on Compilers and Operating Systems for Low Power - COLP, 27/09/2003Publication Instruction buffering exploration for low energy embedded processors
Proceedings paper2003, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Proc. 13th Int. Workshop, 10/09/2003, p.409-419Publication Instruction buffering exploration for low energy embedded processors
Journal article2005, Journal of Embedded Computing (JEC), (1) 3, p.341-351Publication Intermediate variable elimination in a global context for a 3D multimedia application
Proceedings paper2003-07, IEEE International Conference on Multimedia, 6/07/2003, p.73-76Publication L0 buffer energy optimisation through scheduling and exploration
Proceedings paper2004-03, Proceedings of the ACM Symposium on Applied Computing, p.905-906Publication L0 cluster synthesis and operation shuffling
Proceedings paper2004-09, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - PATMOS, 15/09/2004, p.311-321Publication Low power coarse-grained reconfigurable instruction set processor
Proceedings paper2003, Field-Programmable Logic and Applications, 1/09/2003, p.230-239Publication Methodology for building processor design space exploration
Proceedings paper2005, Digest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3, 20/03/2005Publication Optimizing a 3D image reconstruction algorithm: analyzing the capabilities of modern compilers
Proceedings paper2002, IEEE Workshop on Signal Processing Systems - SIPS, 16/10/2002, p.246-251Publication Power estimation approach of dynamic data storage on a hardware software boundary level
Proceedings paper2003-09, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Proc. 13th Int. Workshop, 10/09/2003, p.289-298Publication Reconfigurable instruction set processors from a hardware/software perspective
Journal article2002, IEEE Trans. Software Engineering, (28) 9, p.847-862Publication Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications
Journal article2003, ACM Transactions on Design Automation of Electronic Systems, (8) 1, p.125-139