Browsing by Author "Fasthuber, Robert"
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Publication A programmable low energy massive-parallel architecture for wireless communication systems
Oral presentation2011, DATE, Workshop on ArchitecturesPublication A scalable MIMO detector processor with near-ASIC energy efficiency
Journal article2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (23) 10, p.1973-1986Publication A soft-output Near-ML MIMO baseband receiver for 75Mbps+ SDR
Publication Algorithm/architecture co-design for soft-output ML MIMO detector on massive parallel application specific instruction set processors
Publication An energy-efficient architecture template for wireless communication systems
Fasthuber, RobertPHD thesis2012-10Publication An highly-efficient processor template for wireless communication systems
Oral presentation2012, Design. Automation. and Test in Europe Conference - DATE: PhD ForumPublication An highly-efficient programmable MIMO detector architecture for advanced wireless communication
Proceedings paper2010, STW.ICT Conference on Research in Information and Communication Technology, 18/11/2010Publication Architecture exploration for digital decimation filters
Proceedings paper2009-11, Proceedings of IEEE Workshop on Signal Processing Systems - SiPS, 7/11/2009Publication Bounded block parallel lattice reduction algorithm for MIMO-OFDM
Proceedings paper2010, STW.ICT Conference on Research in Information and Communication Technology, 18/11/2010Publication Bounded block parallel lattice reduction algorithm for MIMO-OFDM and its applciation in LTE MIMO receiver
Proceedings paper2010, IEEE Workshop on Signal Processing Systems - SiPS, 5/10/2010Publication Design space exploration of distributed loop buffer architectures with incompatible loop-nest organisation in embedded systems
Journal article2013, Journal of Signal Processing Systems, 72, p.69-85Publication Early exploration of partitioning trade-offs for heterogeneous MPSoCs
Proceedings paper2011, Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems - ACACES, 10/07/2011Publication Energy impact in the design space exploration of loop buffer schemes in embedded systems
Proceedings paper2013, IFIP International Conference on VLSI - VLSI-SoC, 6/10/2013, p.216-221Publication Energy-efficient run-time scalable soft-output SSFE MIMO detector architectures
Publication Exploiting fine precision information to guide data-flow mapping
Proceedings paper2010, Proceedings of the 47th ACM/IEEE Design Automation Conference - DAC, 13/06/2010, p.248-253Publication Exploration of soft-output MIMO detector implementations on massive parallel processors
Publication High level analysis of trade-offs across different partitioning schemes for wireless applications
Proceedings paper2011, IEEE Workshop on Signal Processing Systems - SIPS, 4/10/2011Publication Low-power run-time scalable MIMO detector architectures