Browsing by Author "Guo, Jin"

A tool flow for predicting system level timing failures due to interconnect reliability degradation

Analysis and optimization of intra-tile commununication network

Energy/area/delay trade-offs in the physical design of on-chip segmented buses architecture

The analysis of system-level timing failures due to interconnect reliability degradation

The need for connecting system-level design and physical design communication energy optimization

Topology exploration for energy efficient intra-tile communication