Browsing by Author "Gupta, Mohit"
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Publication A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W
Proceedings paper2023, IEEE 49th European Solid-State Circuits Conference (ESSCIRC), SEP 11-14, 2023, p.417-420Publication A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
; ; ; ; ; Journal article2021, IEEE TRANSACTIONS ON ELECTRON DEVICES, (68) 8, p.3819-3825Publication An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs
Journal article2024, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (32) 6, p.1018-1031Publication Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers
Journal article2025, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, (72) 1, p.135-142Publication Challenges with SOT-MRAM integration towards N5 node and beyond
Proceedings paper2022, Conference on DTCO and Computational Patterning, APR 24-MAY 27, 2022, p.1205202Publication CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out
Proceedings paper2022, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, JUN 13-15, 2022, p.451-454Publication Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
; ; ; ; ; Proceedings paper2017, IEEE International Conference on Integrated Circuit Design and Technology - ICICDT, 23/05/2017, p.1-4Publication Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications
Proceedings paper2022, 52nd IEEE European Solid-State Device Research Conference (ESSDERC), SEP 19-22, 2022, p.241-244Publication Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications
Proceedings paper2023-07-21, 56th IEEE International Symposium on Circuits and Systems (ISCAS), MAY 21-25, 2023Publication Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Proceedings paper2017, 47th European Solid-State Device Research Conference - ESSDERC, 11/09/2017, p.256-259Publication Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
Journal article2023, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, (70) 3, p.733-746Publication Feasibility analysis of embedded MRAM solutions at advanced process nodes
Proceedings paper2022, 6th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), MAR 06-09, 2022, p.73-75Publication Field-Free Spin-Orbit Torque Driven Switching of Perpendicular Magnetic Tunnel Junction through Bending Current
Journal article2023, NANO LETTERS, (23) 12, p.5482-5489Publication First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories
; ; ; ; ; Proceedings paper2022, International Electron Devices Meeting (IEDM), DEC 03-07, 2022Publication High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node
Proceedings paper2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020Publication Impact of interconnects enhancement on SRAM design beyond 5nm technology node
Proceedings paper2023, 56th IEEE International Symposium on Circuits and Systems (ISCAS), MAY 21-25, 2023Publication Magnetic Domain Wall Memory: A DTCO study for Memory Applications
Proceedings paper2023, IEEE 53rd European Solid-State Device Research Conference (ESSDERC), SEP 11-14, 2023, p.41-44Publication Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices
Journal article2022, ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, (21) 1, p.Art. 3Publication Novel forksheet device architecture as ultimate logic scaling device towards 2nm
Proceedings paper2019, IEEE Electron Devices Meeting - IEDM, 9/12/2019, p.871-874Publication Optimization of read and write performance of SRAMs for node 5nm and beyond
Proceedings paper2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 24/02/2019, p.1096203