Browsing by Author "Loup, V."

Now showing 1 - 3 of 3

200 mm Germanium-on-insulator(GeOI) by smart cut technology and recent GeOI MOSFETs achievements

Akatsu, T.
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Deguet, C.
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Sanchez, L.
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Richtarch, C.
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Allibert, F.
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Letertre, F.
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Mazure, C.
Proceedings paper
2005, Proceedings of the IEEE International SOI Conference, 3/10/2005, p.137-138
CFET channel stack fabrication by wafer-to-wafer bonding and BESOI donor dismounting

Tchouflian, Pauline
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Barge, D.
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Hartmann, J.M.
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Kerdilès, S.
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Vincent, Larrey
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Fournel, Frank
Journal article
2026, MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 214, p.110826
Ultimate Layer Stacking Technology for High Density Sequential 3D Integration

Radu, I.
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Nguyen, B-Y.
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Chang, C-H.
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Neve, C. Roda
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Gaudin, G.
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Besnard, G.
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Batude, P.
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Loup, V.
Proceedings paper
2023, International Electron Devices Meeting (IEDM), 2023-12-09