Browsing by Author "Masselos, Kostas"
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Publication A MATLAB vectorizing compiler targeting application-specific instruction set processors
Journal article2017, ACM Transactions on Design Automation of Electronic Systems, (22) 2, p.Art.32Publication A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints
Proceedings paper1999, Proceedings IEEE International Symposium on Low Power Electronics and Design - ISLPED, 16/08/1999, p.270-272Publication A performance oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors
Proceedings paper1999, Proceedings IEEE Workshop on Signal Processing Systems - SIPS; October 1999; Taipeh, Taiwan., p.261-270Publication A specification refinement methodology for power efficient partitioning of data-dominated algorithms within performance constraints
Journal article2000, J. VLSI Signal Processing, (26) 3, p.291-318Publication Code size effects of power optimizing code transformations for embedded multimedia applications
Proceedings paper1999, Proceedings IEEE Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS; October 1999; Kos, Greece., p.61-70Publication Combined application of data transfer and storage optimizing transformations and subword parallelism exploitation for power consumption and execution time reduction in VLIW multimedia processors
Journal article2004-05, Journal of VLSI Signal Processing, (37) 1, p.53-73Publication Effect of data transfer and storage optimization on design quality factors of multimedia algorithms realized on instruction set processors
Proceedings paper2001, Proceedings IEEE Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS; September 2001; Yverdon-les-Bains,, p.3.3.1-3.3.10Publication Hardware building blocks of a mixed granularity reconfigurable system-on-chip platform
Publication Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors
Proceedings paper1999, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design; Como, Italy; 4-5 March 1999., p.52-60Publication Memory hierarchy layer assessment for data re-use exloitation in multimedia algorithms realized on predefined processor architectures
Proceedings paper2001, Proceedings International Conference on Electronic Circuits and Systems - ICECS; September 2001; Malta., p.285-288Publication Realization of wireless multimedia communication systems on reconfigurable platforms
Journal article2003, Journal of Systems Architecture, (49) 4_6, p.155-175Publication Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec
Journal article1999, Journal of System Architecture, (45) 10, p.791-808Publication Strategy for power-efficient design of parallel systems
Journal article1999, IEEE Trans. VLSI Systems, (7) 2, p.258-265Publication System-level modeling of dynamically reconfigurable hardware with SystemC
Proceedings paper2003, Proceedings International Symposium on Parallel and Distributed Processing, 22/04/2003, p.174-181Publication System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors
Proceedings paper1999, Proceedings International Conference on Electronics, Circuits and Systems - ICECS, 5/09/1999, p.1733-1736Publication Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: a pre-compiler for multimedia applications
Journal article2003, Design Automation for Embedded systems, (8) 1, p.51-86Publication SystemC and OCAPI-XL based system-level design for reconfigurable systems-on-chip
Proceedings paper2004-09, Forum on Specification & Design Languages, 13/09/2004, p.428-439