Browsing by Author "Mayahinia, Mahta"

Analyzing the Electromigration Challenges of Computation in Resistive Memories

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes

Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus