Browsing by Author "Mei, Bingfeng"
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Publication A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Proceedings paper2007-09, International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES, 30/09/2007, p.229-237Publication A coarse-grained reconfigurable architecture template and its compilation techniques
Mei, BingfengPHD thesis2005-01Publication A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems
Proceedings paper2000, Proceedings 11th ProRISC Workshop on Circuits, Systems, and Signal Processing, 29/11/2000, p.405-411Publication ADRES & DRESC: architecture and compiler for coarse-grain reconfigurable processors
Publication ADRES reconfigurable architecture and its compilation techniques
Mei, BingfengOral presentation2005, The Future of Configurable HardwarePublication ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix
Proceedings paper2003, 13th International Conference on Field-Programmable Logic and Applications, 1/09/2003, p.61-70Publication An efficient memory organization for high-ILP inner modem baseband SDR processors
Journal article2010, Journal of Signal Processing Systems, (61) 2, p.157-179Publication Architecture exploration for a reconfigurable architecture template
Journal article2005, IEEE Design & Test, (22) 2, p.90-101Publication Custom implementation of the coarse-grained reconfigurable ADRES architectures for multimedia purposes
Publication Design and optimization of dynamically reconfigurable embedded systems
Mei, BingfengOral presentation2001, 1st International Conf. on Engineering of Reconfigurable Systems and Algorithms - ERSAPublication Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
Proceedings paper2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 16/02/2003, p.1224-1229Publication Design style case study for computer nodes of a heterogeneous NoC platform
Proceedings paper2004-12, 25th IEEE International Real-Time Systems Symposium, 5/12/2004, p.104-113Publication Development of a design framework for platform-independent networked reconfiguration of software and hardware
Proceedings paper2001, Proceedings of the 11th International Conference on Field-Programmable Logic and Applications; August 2001; Belfast, UK., p.264-274Publication DRESC: A retargetable compiler for Coarse-Grained reconfigurable architectures
Proceedings paper2002, IEEE International Conference on Field Programmable Technology - FPT, 16/12/2002, p.166-173Publication Energy aware architecture exploration of a CGRA template
Oral presentation2005, HiPEAC ACACES Summer SchoolPublication Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Proceedings paper2003, Design, Automation and Test in Europe Conference and Exhibition - DATE, 3/03/2003, p.296-301Publication Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Journal article2003-09, IEE Proceedings: Computer & Digital Techniques, (150) 5, p.255-261Publication Implementation of a coarse-grained reconfigurable media processor for AVC decoder
Journal article2008, Journal of VLSI Signal Processing Systems, (51) 3, p.225-243Publication Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
Proceedings paper2004, IEEE International Conference on Field Programmable Technology - FPT, 6/12/2004