Browsing by Author "Nuzzo, Pierluigi"
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Publication A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS
Proceedings paper2009, IEEE Radio Frequency Integrated Circuits Symposium - RFIC, 7/06/2009, p.321-324Publication A 2mm2 0.1-5GHz SDR receiver in 45nm digital CMOS
Proceedings paper2009, IEEE International Solid-State Circuits Conference - ISSCC, 8/02/2009, p.408-409Publication A 2mm2 0.1-5GHz software defined radio receiver in 45nm digital CMOS
Journal article2009, IEEE Journal of Solid-State Circuits, (44) 12, p.3486-3498Publication A 6-bit 50-MS/s hhreshold configuring SAR ADC in 90-nm digital CMOS
Publication A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
Publication A CMOS ultra-wideband receiver for low data-rate communication
; ; ; Journal article2007, IEEE Journal of Solid-State Circuits, (42) 11, p.2515-2527Publication An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation
Proceedings paper2010, Design Automation and Test in Europe Conference - DATE, 8/03/2010, p.697-701Publication An 820 μW 9b 40MS/s noise-tolerant dynamic SAR ADC in 90nm digital CMOS
Proceedings paper2008-02, IEEE International Solid-State Circuits Conference - ISSCC, 3/02/2008, p.238-239Publication Architectural exploration and design of time-interleaved SAR arrays for low-power and high speed A/D converters
Journal article2009, IEICE Transactions on Electronics, (E92-C) 6, p.843-851Publication Mixed-signal design space exploration of time-interleaved A/D converters for ultra-wide band applications
Proceedings paper2008, Design, Automation and Test in Europe Conference - DATE, 10/03/2008, p.1390-1393Publication Noise analysis of regenerative comparators for reconfigurable ADC architectures
Journal article2008, IEEE Transactions on Circuits and Systems I, (55) 6, p.1441-1454