Browsing by Author "Sateesan, Arish"
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Publication A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs
Publication An Analysis of the Hardware-Friendliness of AMQ Data Structures for Network Security
Publication DASH: Design Automation for Synthesis and Hardware Generation for CNN
Publication Hardware-oriented optimization of Bloom filter algorithms and architectures for ultra-high-speed lookups in network applications
Journal article2022, MICROPROCESSORS AND MICROSYSTEMS, 93, p.Art. 104619Publication Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications
Proceedings paper2020, 23rd Euromicro Conference on Digital System Design (DSD), AUG 26-28, 2020, p.262-269Publication Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA
Proceedings paper2021, 24th Euromicro Conference on Digital System Design (DSD), SEP 01-03, 2021, p.347-354Publication Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware
Publication SoK - Network Intrusion Detection on FPGA
Proceedings paper2022, 11th International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE), DEC 10-13, 2021, p.242-261Publication Speed Records in Network Flow Measurement on FPGA
Proceedings paper2021, 31st International Conference on Field-Programmable Logic and Applications (FPL), AUG 30-SEP 03, 2021, p.219-224