Browsing by Author "Schaumont, Patrick"
- Results per page
- Sort Options
Publication A 10Mbit/s upstream cable modem with automatic equalization
Proceedings paper1999, 36th Design Automation Conference. Proceedings, 21/06/1999, p.337-340Publication A hardware virtual machine for networked reconfiguration
Proceedings paper2000, Proceedings 11th International Workshop on Rapid System Prototyping - RSP. "Shortening the Path from Specification to Prototype", 21/06/2000, p.194-199Publication A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems
Proceedings paper2000, Proceedings 11th ProRISC Workshop on Circuits, Systems, and Signal Processing, 29/11/2000, p.405-411Publication A methodology and design environment for DSP ASIC fixed point refinement
Proceedings paper1999, Proceedings Design and Test in Europe Conference; March 1999; Munich, Germany., p.271-276Publication A new algorithm for elimination of common subexpressions
Journal article1999, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, (18) 1, p.58-68Publication A programming environment for the design of complex high speed ASICs
Proceedings paper1998, Proceedings of the 35th Design Automation Conference - DAC, 15/06/1998, p.315-320Publication A quick safari through the reconfiguration jungle
;Schaumont, Patrick ;Verbauwhede, Ingrid ;Keutzer, K.Sarrafzadeh, M.Proceedings paper2001, Proceedings of the 38th Design Automation Conference;, p.172-177Publication A scalable architecture to support networked reconfiguration
Proceedings paper1999, ProRISC/IEEE 10th Annual Workshop on `Circuits and Systems and Signal Processing', 25/11/1999, p.677-683Publication A SW/HW interface API for Java/FPGA co-designed applets
Proceedings paper2001, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, p.677-684Publication A technique for combined virtual prototyping and hardware design
Proceedings paper1998, Proceedings 9th IEEE International Workshop on Rapid System Prototyping - RSP, 3/06/1998, p.156-161Publication Adding reconfigurable logic to SOC designs
;Gupta, B. ;Parviainen, J. A. ;Schaumont, Patrick ;Tanurhan, Y.Roy, K.Journal article2001, IEEE Design & Test of Computers, (18) 4, p.65-71Publication An object-oriented programming approach for hardware design
Proceedings paper1999, IEEE Computer Society Workshop on VLSI; April 1999; Orlando, FL, USA., p.68-73Publication Building a virtual framework for networked reconfigurable hardware and software objects
Journal article2002, Journal of Supercomputing, (21) 2, p.131-144Publication Building a virtual framework for networked reconfigurable hardware and software objects
Proceedings paper2000, International Conference on Parallel and Distributed Processing Techniques and Applications; June 2000; Las Vegas, NV, USA., p.3046-52Publication C++ based system design of a 72 Mb/s OFDM tranceiver for wireless LAN
Proceedings paper2001, Proceedings IEEE 2001 Custom Integrated Circuits Conference, 6/05/2001, p.433-439Publication Design of a secure, intelligent, and reconfigurable web cam using a C based system design flow
Proceedings paper2001, Conference Record of the 35th Asilomar Conference on Signals, Systems and Computers, 4/11/2001, p.463-467Publication Design space exploration of all-digital symbol timing adjustment architectures
Proceedings paper1996, Proceedings IEEE 4th Symposium on Communications and Vehicular Technology in the Benelux, 7/10/1996, p.88-93Publication Development of a design framework for platform-independent networked reconfiguration of software and hardware
Proceedings paper2001, Proceedings of the 11th International Conference on Field-Programmable Logic and Applications; August 2001; Belfast, UK., p.264-274Publication Digital upconversion architecture for quadrature modulators
Proceedings paper1996, VLSI Signal Processing IX, 30/10/1996, p.315-324Publication Dynamical analysis of all digital symbol timing recovery in twisted pair broadband receivers
Proceedings paper1997, 13th International Conference on Digital Signal Processing - DSP, 2/07/1997, p.1055-1058
- «
- 1 (current)
- 2
- 3
- »