Browsing by Author "Sinha, S."

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Buried Bitline for sub-5nm SRAM Design

Mathur, R.
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Bhargava, M.
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Annamalai, S.
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Chong, Y. K.
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Sinha, S.
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Cline, B.
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Kulkarni, J. P.
Proceedings paper
2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020
Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm

Prasad, D.
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Nibhanupudi, S.
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Das, S.
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Zografos, Odysseas
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Chehab, Bilal
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Sarkar, Satadru
Proceedings paper
2019, IEEE International Electron Devices Meeting - IEDM 2019, 9/12/2019, p.446-449