Browsing by Author "Yamamoto, Takaya"
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Publication A 5mm2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver
Proceedings paper2010, IEEE International Solid-State Circuits Conference - ISSCC, 7/02/2010, p.458-459Publication A 5mm2 40nm LP CMOS 0.1-to-6GHz multistandard transceiver
Proceedings paper2010-06, SDR Forum European Reconfigurable Radio Technologies Workshop and Product Exposition, 23/06/2010Publication A 5mm2 40nm LP CMOS transceiver for a software-defined radio platform
Journal article2010, IEEE Journal of Solid-State Circuits, (45) 12, p.2794-2806Publication A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation
Journal article2015, IEEE Journal of Solid-State Circuits, (50) 9, p.2002-2011Publication A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range
Journal article2014, IEEE Journal of Solid-State Circuits, (49) 5, p.1173-1183Publication A 70dB DR 10b 0-to-80MS/s current integrating SAR ADC with adaptive dynamic range