Browsing by author "Kim, Myungsun"

Now showing items 1-3 of 3

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019)
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Ritzenthaler, Romain; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Vaisman Chasin, Adrian; Kenis, Karine; Devriendt, Katia; Mannaert, Geert; Dekkers, Harold; Dangol, Anish; Lin, Yongjin; Sun, Shiyu; Chen, Zhebo; Kim, Myungsun; Chen, ShiChung; Machillot, Jerome; Mitard, Jerome; Yoshida, Naomi; Kim, Namsung; Mocuta, Dan; Horiguchi, Naoto (2018)
Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration

Mertens, Hans; Ritzenthaler, Romain; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Schulze, Andreas; Dentoni Litta, Eugenio; Chew, Soon Aik; Devriendt, Katia; Chiarella, Thomas; Demuynck, Steven; Yakimets, Dmitry; Jang, Doyoung; Spessot, Alessio; Eneman, Geert; Dangol, Anish; Lagrain, Pieter; Bender, Hugo; Sun, Shiyu; Korolik, Michael; Kioussis, D.; Kim, Myungsun; Bu, Kyung-Ho; Chen, Shih Chung; Cogorno, Matt; Devrajan, J.; Machillot, Jerome; Yoshida, Naomi; Kim, Namsung; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017)

Browsing by author "Kim, Myungsun"

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors ﻿

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization ﻿

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration ﻿

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration