Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

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Authors
Ritzenthaler, Romain; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Vaisman Chasin, Adrian; Kenis, Karine; Devriendt, Katia; Mannaert, Geert; Dekkers, Harold; Dangol, Anish; Lin, Yongjin; Sun, Shiyu; Chen, Zhebo; Kim, Myungsun; Chen, ShiChung; Machillot, Jerome; Mitard, Jerome; Yoshida, Naomi; Kim, Namsung; Mocuta, Dan; Horiguchi, Naoto
Conference
IEEE International Electron Devices Meeting - IEDM
Title
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Publication type
Proceedings paper
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