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Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Publication:
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Date
2018
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Ritzenthaler, Romain
;
Mertens, Hans
;
Pena, Vanessa
;
Santoro, Gaetano
;
Vaisman Chasin, Adrian
;
Kenis, Karine
;
Devriendt, Katia
;
Mannaert, Geert
;
Dekkers, Harold
;
Dangol, Anish
;
Lin, Yongjin
;
Sun, Shiyu
;
Chen, Zhebo
;
Kim, Myungsun
;
Chen, ShiChung
;
Machillot, Jerome
;
Mitard, Jerome
;
Yoshida, Naomi
;
Kim, Namsung
;
Mocuta, Dan
;
Horiguchi, Naoto
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Abstract
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2177
since deposited on 2021-10-26
Acq. date: 2025-10-23
Citations
Metrics
Views
2177
since deposited on 2021-10-26
Acq. date: 2025-10-23
Citations