Browsing by author "Mei, Bingfeng"
Now showing items 1-20 of 23
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A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Vander Aa, Tom; De Sutter, Bjorn; Mei, Bingfeng (2007-09) -
A coarse-grained reconfigurable architecture template and its compilation techniques
Mei, Bingfeng (2005-01) -
A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems
Mei, Bingfeng; Schaumont, Patrick; Vernalde, Serge (2000) -
A tightly coupled VLIW/reconfigurable matrix and its modulo scheduling technique
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; Lauwereins, Rudy (2005) -
ADRES & DRESC: architecture and compiler for coarse-grain reconfigurable processors
Mei, Bingfeng; Berekovic, Mladen; Mignolet, Jean-Yves (2007) -
ADRES reconfigurable architecture and its compilation techniques
Mei, Bingfeng (2005) -
ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; De Man, Hugo; Lauwereins, Rudy (2003) -
An efficient memory organization for high-ILP inner modem baseband SDR processors
De Sutter, Bjorn; Allam, Osman; Raghavan, Praveen; Vandebriel, Roeland; Cappelle, Hans; Vander Aa, Tom; Mei, Bingfeng (2010) -
Architecture exploration for a reconfigurable architecture template
Mei, Bingfeng; Lambrechts, Andy; Verkest, Diederik; Mignolet, Jean-Yves; Lauwereins, Rudy (2005) -
Custom implementation of the coarse-grained reconfigurable ADRES architectures for multimedia purposes
Veredas, Francisco-Javier; Scheppler, Michael; Moffat, Will; Mei, Bingfeng (2005) -
Design and optimization of dynamically reconfigurable embedded systems
Mei, Bingfeng (2001) -
Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; Lauwereins, Rudy (2004) -
Design style case study for computer nodes of a heterogeneous NoC platform
Lambrechts, Andy; Vander Aa, Tom; Jayapala, Murali; Leroy, Anthony; Talavera, Guillermo; Shickova, Adelina; Barat, Francisco; Mei, Bingfeng; Catthoor, Francky; Verkest, Diederik; Deconinck, Geert; Corporaal, Henk; Robert, Frederic; Carrabina Bordoll, Jordi (2004-12) -
Development of a design framework for platform-independent networked reconfiguration of software and hardware
Ha, Y.; Mei, Bingfeng; Schaumont, Patrick; Vernalde, Serge; Lauwereins, Rudy; De Man, Hugo (2001) -
DRESC: A retargetable compiler for Coarse-Grained reconfigurable architectures
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; De Man, Hugo; Lauwereins, Rudy (2002) -
Energy aware architecture exploration of a CGRA template
Lambrechts, Andy; Raghavan, Praveen; Jayapala, Murali; Mei, Bingfeng; Verkest, Diederik (2005) -
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; De Man, Hugo; Lauwereins, Rudy (2003) -
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Mei, Bingfeng; Vernalde, Serge; Verkest, Diederik; De Man, Hugo; Lauwereins, Rudy (2003-09) -
Implementation of a coarse-grained reconfigurable media processor for AVC decoder
Mei, Bingfeng; De Sutter, Bjorn; Vander Aa, Tom; Wouters, Marysse; Kanstein, Andreas; Dupont, Steven (2008) -
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
Wilton, Steve J. E.; Kafafi, Noha; Mei, Bingfeng; Vernalde, Serge (2004)