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Articles
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Publication:
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
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Date
2003-09
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Mei, Bingfeng
;
Vernalde, Serge
;
Verkest, Diederik
;
De Man, Hugo
;
Lauwereins, Rudy
Journal
IEE Proceedings: Computer & Digital Techniques
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1975
since deposited on 2021-10-15
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last month
Acq. date: 2025-12-13
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Metrics
Views
1975
since deposited on 2021-10-15
1
last month
Acq. date: 2025-12-13
Citations