Browsing by author "Sathanur, Ashoka"
Now showing items 1-6 of 6
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Activity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs
Sathanur, Ashoka; Huisken, Jos; Stuijt, Jan; de Groot, Harmke (2010) -
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Kakoee, Mohammed Reza; Sathanur, Ashoka; Pullini, Antonio; Huisken, Jos; Benini, Luca (2010) -
Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing
Sathanur, Ashoka; Ashouei, Maryam; Huisken, Jos (2010) -
Leakage control in SoCs
Raghavan, Praveen; Sathanur, Ashoka; Cosemans, Stefan; Dehaene, Wim (2012) -
Leakage current mechanisms and estimation in memories and logic
Sathanur, Ashoka; Raghavan, Praveen; Cosemans, Stefan; Dehaene, Wim (2012) -
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications
Artes, A.; Ayala, J.; Sathanur, Ashoka; Huisken, Jos; Catthoor, Francky (2011)