Browsing by author "Harada, N."

Now showing items 1-3 of 3

    • 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices 

      Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019)

    • DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM 

      Matagne, Philippe; Nakamura, H.; Kim, Min-Soo; Kikuchi, Yoshiaki; Huynh Bao, Trong; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Boemmels, Juergen; Mallik, Arindam; Altamirano Sanchez, Efrain; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Porret, Clément; Mocuta, Dan; Harada, N.; Matsuoka, F. (2018)

    • Interconnects for scaled SRAM with vertical Surrounded Gate Transistors (SGT) 

      Boemmels, Juergen; Harada, N.; Kim, Min-Soo; Mitard, Jerome; Kikuchi, Yoshiaki; Li, Waikin; Tao, Zheng; Puliyalil, Harinarayanan; Devriendt, Katia; Lorant, Christophe; Le, Quoc Toan; Kesters, Els; Jourdan, Nicolas; El-Mekki, Zaid; Teugels, Lieve; van der Veen, Marleen; Li, Y.; Nakamura, H.; Mocuta, Dan; Masuoka, F. (2019)