Browsing by author "Rooseleer, Bram"
Now showing items 1-5 of 5
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A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in -Memory Analog Matrix -Vector-Multiplier for DNN Acceleration
Papistas, Ioannis; Cosemans, Stefan; Rooseleer, Bram; Doevenspeck, Jonas; Na, Myung Hee; Mallik, Arindam; Debacker, Peter; Verkest, Diederik (2021) -
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
Rooseleer, Bram; Cosemans, Stefan; Dehaene, Wim (2011) -
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
Rooseleer, Bram; Cosemans, Stefan; Dehaene, Wim (2012) -
Circuit design for bas compatibility in novel FinFET-based floating body RAM
Poliakov, Pavel; Anchlia, Ankur; Garcia Bardon, Marie; Rooseleer, Bram; De Wachter, Bart; Collaert, Nadine; van der Zanden, Koen; Dehaene, Wim; Verkest, Diederik; Miranda Corbalan, Miguel (2010) -
Circuit design for bias compatibility investigation of bulk FinFET based floating body RAM
Anchlia, Ankur; Garcia Bardon, Marie; Poliakov, Pavel; Rooseleer, Bram; De Wachter, Bart; Collaert, Nadine; van der Zanden, Koen; Miranda Corbalan, Miguel; Dehaene, Wim; Verkest, Diederik (2009)