Browsing by author "Takeoka, S."
Now showing items 1-2 of 2
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Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Witters, Liesbeth; Mitard, Jerome; Veloso, Anabela; Hikavyy, Andriy; Franco, Jacopo; Kauerauf, Thomas; Cho, Moon Ju; Schram, Tom; Sebaai, Farid; Yamaguchi, Shinpei; Takeoka, S.; Fukuda, Masahiro; Wang, Wei-E; Duriez, Blandine; Eneman, Geert; Loo, Roger; Kellens, Kristof; Tielens, Hilde; Favia, Paola; Rohr, Erika; Hellings, Geert; Bender, Hugo; Roussel, Philippe; Crabbe, Yvo; Brus, Stephan; Mannaert, Geert; Kubicek, Stefan; Devriendt, Katia; De Meyer, Kristin; Ragnarsson, Lars-Ake; Steegen, An; Horiguchi, Naoto (2011) -
High performance Si.45Ge.55 implant free quantum well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
Yamaguchi, Shinpei; Witters, Liesbeth; Mitard, Jerome; Eneman, Geert; Hellings, Geert; Fukuda, Masahiro; Hikavyy, Andriy; Loo, Roger; Veloso, Anabela; Crabbe, Yvo; Rohr, Erika; Favia, Paola; Bender, Hugo; Takeoka, S.; Vellianitis, Georgios; Wang, Wei-E; Ragnarsson, Lars-Ake; De Meyer, Kristin; Steegen, An; Horiguchi, Naoto (2011)