Now showing items 1-3 of 3

    • A systematic study of trade-offs in engineering a locally strained pMOSFET 

      Nouri, Faran; Verheyen, Peter; Washington, Lori; Moroz, Victor; De Wolf, Ingrid; Kawaguchi, S.; Biesemans, Serge; Schreutelkamp, Rob; Kim, Y.; Shen, M.; Xu, X.; Rooyackers, Rita; Jurczak, Gosia; Eneman, Geert; De Meyer, Kristin; Smith, L.; Pramanik, D.; Forstner, H.; Thirupapuliyur, S.; Higashi, G. (2004)
    • Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology 

      Guo, Wei; Moroz, Victor; Van der Plas, Geert; Choi, M.; Redolfi, Augusto; Smith, L.; Eneman, Geert; Van Huylenbroeck, Stefaan; Su, P.D.; Ivankovic, Andrej; De Wachter, Bart; Debusschere, Ingrid; Croes, Kris; De Wolf, Ingrid; Mercha, Abdelkarim; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2013)
    • Layout impact on the performance of a locally strained PMOSFET 

      Eneman, Geert; Verheyen, Peter; Rooyackers, Rita; Nouri, Faran; Washington, Lori; Degraeve, Robin; Kaczer, Ben; Moroz, Victor; De Keersgieter, An; Schreutelkamp, Rob; Kawaguchi, M.; Kim, Y.; Samoilov, A.; Smith, L.; Absil, Philippe; De Meyer, Kristin; Jurczak, Gosia; Biesemans, Serge (2005)