Browsing by author "Bauer, F."
Now showing items 1-5 of 5
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A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
von Arnim, Klaus; Augendre, Emmanuel; Pacha, C.; Schulz, Thomas; San, Kemal Tamer; Bauer, F.; Nackaerts, Axel; Rooyackers, Rita; Vandeweyer, Tom; Degroote, Bart; Collaert, Nadine; Dixit, Abhisek; Singanamalla, Raghunath; Xiong, W.; Marshall, A.; Cleavelin, C.R.; Schrüfer, K.; Jurczak, Gosia (2007) -
Analog design challenges and trade-offs using emerging materials and devices
Fulde, Michael; Mercha, Abdelkarim; Gustin, Cedric; Parvais, Bertrand; Subramanian, Vaidy; von Arnim, Klaus; Bauer, F.; Schruefer, K.; Schmitt-Landsiedel, D.; Knoblinger, Gerald (2007-09) -
Layout options for stability tuning of SRAM cells in multi-gate=FET technologies
Bauer, F.; von Arnim, Klaus; Pacha, C.; Schultz, T.; Fulde, M.; Nackaerts, Axel; Jurczak, Gosia; Xiong, W.; San, K.T.; Cleavelin, C.R.; Schrüfer, K.; Georgakos, G.; Schmitt-Landsiedel, D. (2007) -
Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
Collaert, Nadine; von Arnim, Klaus; Rooyackers, Rita; Vandeweyer, Tom; Mercha, Abdelkarim; Parvais, Bertrand; Witters, Liesbeth; Nackaerts, Axel; Altamirano Sanchez, Efrain; Demand, Marc; Hikavyy, Andriy; Demuynck, Steven; Devriendt, Katia; Bauer, F.; Ferain, Isabelle; Veloso, Anabela; De Meyer, Kristin; Biesemans, Serge; Jurczak, Gosia (2008) -
Low-voltage scaled 6T FinFET SRAM cells
Collaert, Nadine; von Arnim, Klaus; Rooyackers, Rita; Vandeweyer, Tom; Mercha, Abdelkarim; Parvais, Bertrand; Witters, Liesbeth; Nackaerts, Axel; Altamirano Sanchez, Efrain; Demand, Marc; Hikavyy, Andriy; Demuynck, Steven; Devriendt, Katia; Bauer, F.; Ferain, Isabelle; Veloso, Anabela; De Meyer, Kristin; Biesemans, Serge; Jurczak, Gosia (2010-08)