Browsing by imec author "acb2fe8014f578853db6c49fce8abc071054efb8"
Now showing items 1-4 of 4
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Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020) -
DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies
Garcia Bardon, Marie; Wuytens, Pieter; Ragnarsson, Lars-Ake; Mirabelli, Gioele; Jang, Doyoung; Willems, Geert; Mallik, Arindam; Spessot, Alessio; Ryckaert, Julien; Parvais, Bertrand (2020) -
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Ahmed, Zubair; Afzalian, Aryan; Schram, Tom; Jang, Doyoung; Verreck, Devin; Smets, Quentin; Schuddinck, Pieter; Chehab, Bilal; Sutar, Surajit; Arutchelvan, Goutham; Soussou, Assawer; Asselberghs, Inge; Spessot, Alessio; Radu, Iuliana; Parvais, Bertrand; Ryckaert, Julien; Na, Myung Hee (2020) -
NANOWIRE & NANOSHEET FETS FOR ADVANCED ULTRA-SCALED, HIGH-DENSITY LOGIC AND MEMORY APPLICATIONS
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Jang, Doyoung; Huynh-Bao, T.; Vaisman Chasin, Adrian; Simoen, Eddy; De Keersgieter, An; Horiguchi, Naoto (2020)