Browsing by author "Yamamoto, Takaya"
Now showing items 1-6 of 6
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A 5mm2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver
Ingels, Mark; Giannini, Vito; Borremans, Jonathan; Mandal, Gunjan; Debaillie, Bjorn; Van Wesemael, Peter; Sano, Tomohiro; Yamamoto, Takaya; Hauspie, Dries; Van Driessche, Joris; Craninckx, Jan (2010) -
A 5mm2 40nm LP CMOS 0.1-to-6GHz multistandard transceiver
Ingels, Mark; Giannini, Vito; Borremans, Jonathan; Mandal, Gunjan; Debaillie, Bjorn; Van Wesemael, Peter; Sano, Tomohiro; Yamamoto, Takaya; Hauspie, Dries; Van Driessche, Joris; Craninckx, Jan (2010-06) -
A 5mm2 40nm LP CMOS transceiver for a software-defined radio platform
Ingels, Mark; Giannini, Vito; Borremans, Jonathan; Mandal, Gunjan; Debaillie, Bjorn; Van Wesemael, Peter; Sano, Tomohiro; Yamamoto, Takaya; Hauspie, Dries; Van Driessche, Joris; Craninckx, Jan (2010) -
A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation
Verbruggen, Bob; Tsouhlarakis, Jorgo; Yamamoto, Takaya; Iriguchi, Masao; Martens, Ewout; Craninckx, Jan (2015) -
A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range
Malki, Badr; Yamamoto, Takaya; Verbruggen, Bob; Wambacq, Piet; Craninckx, Jan (2014) -
A 70dB DR 10b 0-to-80MS/s current integrating SAR ADC with adaptive dynamic range
Malki, Badr; Yamamoto, Takaya; Verbruggen, Bob (2012)