Browsing by author "Sharan, Neha"
Now showing items 1-4 of 4
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Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery
Spessot, Alessio; Sharan, Neha; Oh, Hyungrock; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Mallik, Arindam; De Keersgieter, An; Parvais, Bertrand; Sherazi, Yasser; Machkaoutsan, Vladimir; Kim, Cheolgyu; Fazan, Pierre; Mocuta, Dan; Mocuta, Anda; Horiguchi, Naoto (2018-01) -
Device challenges for logic scaling for sub-5 nm node
Jang, Doyoung; Garcia Bardon, Marie; Yakimets, Dmitry; Schuddinck, Pieter; Ragnarsson, Lars-Ake; Sharan, Neha; Parvais, Bertrand; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2018) -
Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies
Rawat, Amita; Sharan, Neha; Jang, Doyoung; Chiarella, Thomas; Bufler, Fabian; Catthoor, Francky; Parvais, Bertrand; Ganguly, Udayan (2021) -
Ge Devices: a potential candidate for sub-5nm nodes?
Sharan, Neha; Shaik, Khaja Ahmad; Jang, Doyoung; Schuddinck, Pieter; Yakimets, Dmitry; Garcia Bardon, Marie; Mitard, Jerome; Arimura, Hiroaki; Bufler, Fabian; Eneman, Geert; Collaert, Nadine; Parvais, Bertrand; Spessot, Alessio; Mocuta, Anda (2019)