Browsing by author "Chae, Jung Kyu"
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CFET standard-cell design down to 3Track height for node 3nm and below
Sherazi, Yasser; Chae, Jung Kyu; Debacker, Peter; Mattii, Luca; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Spessot, Alessio; Dounde, Amit; Ryckaert, Julien (2019) -
Track height reduction for standard-cell in below 5nm node: How low can you go?
Sherazi, Yasser; Chae, Jung Kyu; Debacker, Peter; Mattii, Luca; Raghavan, Praveen; Gerousis, V.; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Spessot, Alessio; Ryckaert, Julien (2018)