Browsing by author "Nakaei, T"
Now showing items 1-3 of 3
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Design methodology of FinFET devices that meet IC-level HBM ESD targets
Thijs, Steven; Russ, Christian; Tremouilles, David; Linten, Dimitri; Scholz, Mirko; Jurczak, Gosia; Collaert, Nadine; Rooyackers, Rita; Sawada, M; Nakaei, T; Hasebe, T; Duvvury, Charvaka; Gossner, Harald; Groeseneken, Guido (2008-09) -
On-wafer human metal model measurements for system-level ESD analysis on component level
Scholz, Mirko; Linten, Dimitri; Thijs, Steven; Griffoni, Alessio; Sawada, Masanori; Nakaei, T; Hasebe, Takumi; Lafonteese, David; Vashchenko, Vladislav; Vandersteen, Gerd; Hopper, Peter; Meneghesso, Gaudenzio; Groeseneken, Guido (2009-10) -
Self-protection capability of power arrays
Lafonteese, David; Vashchenko, Vladislav; Linten, Dimitri; Scholz, Mirko; Thijs, Steven; Sawada, Masanori; Nakaei, T; Hasebe, Takumi; Hopper, Peter; Groeseneken, Guido (2009-09)