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Methodology for building processor design space exploration

dc.contributor.authorBarat, F.
dc.contributor.authorVander Aa, Tom
dc.contributor.authorJayapala, Murali
dc.contributor.authorDeconinck, G.
dc.contributor.authorLauwereins, Rudy
dc.contributor.authorCorporaal, Henk
dc.date.accessioned2021-10-16T00:44:02Z
dc.date.available2021-10-16T00:44:02Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10059
dc.sourceIIOimport
dc.titleMethodology for building processor design space exploration
dc.typeProceedings paper
dc.contributor.imecauthorVander Aa, Tom
dc.contributor.imecauthorJayapala, Murali
dc.contributor.imecauthorLauwereins, Rudy
dc.contributor.orcidimecVander Aa, Tom::0000-0002-1504-5266
dc.contributor.orcidimecJayapala, Murali::0000-0001-7917-0149
dc.contributor.orcidimecLauwereins, Rudy::0000-0002-3861-0168
dc.source.peerreviewno
dc.source.conferenceDigest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3
dc.source.conferencedate20/03/2005
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - imec
imec.internalnotesDigest of the Workshop: http://www.ece.vill.edu/~deepu/odes/odes-3_digest.pdf


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