dc.contributor.author | Barat, F. | |
dc.contributor.author | Vander Aa, Tom | |
dc.contributor.author | Jayapala, Murali | |
dc.contributor.author | Deconinck, G. | |
dc.contributor.author | Lauwereins, Rudy | |
dc.contributor.author | Corporaal, Henk | |
dc.date.accessioned | 2021-10-16T00:44:02Z | |
dc.date.available | 2021-10-16T00:44:02Z | |
dc.date.issued | 2005 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/10059 | |
dc.source | IIOimport | |
dc.title | Methodology for building processor design space exploration | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Vander Aa, Tom | |
dc.contributor.imecauthor | Jayapala, Murali | |
dc.contributor.imecauthor | Lauwereins, Rudy | |
dc.contributor.orcidimec | Vander Aa, Tom::0000-0002-1504-5266 | |
dc.contributor.orcidimec | Jayapala, Murali::0000-0001-7917-0149 | |
dc.contributor.orcidimec | Lauwereins, Rudy::0000-0002-3861-0168 | |
dc.source.peerreview | no | |
dc.source.conference | Digest of the 3rd Workshop on Optimizations for DSP and Embedded Systems - ODES-3 | |
dc.source.conferencedate | 20/03/2005 | |
dc.source.conferencelocation | San Jose, CA USA | |
imec.availability | Published - imec | |
imec.internalnotes | Digest of the Workshop: http://www.ece.vill.edu/~deepu/odes/odes-3_digest.pdf | |