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Power consumption in reversible logic addressed by a ramp voltage

dc.contributor.authorDe Vos, Alexis
dc.contributor.authorVan Rentergem, Yvan
dc.date.accessioned2021-10-16T01:12:31Z
dc.date.available2021-10-16T01:12:31Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10328
dc.sourceIIOimport
dc.titlePower consumption in reversible logic addressed by a ramp voltage
dc.typeProceedings paper
dc.source.peerreviewno
dc.source.beginpage207
dc.source.endpage216
dc.source.conferenceIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation.15th International Workshop PATMOS
dc.source.conferencedate21/09/2005
dc.source.conferencelocationLeuven Belgium
imec.availabilityPublished - imec
imec.internalnotesLecture Notes in Computer Science - LNCS; Vol. 3728


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