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Optimization of scatterometry parameters for the gate level of the 90nm node

dc.contributor.authorLeray, Philippe
dc.contributor.authorCheng, Shaunee
dc.date.accessioned2021-10-16T02:51:38Z
dc.date.available2021-10-16T02:51:38Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10767
dc.sourceIIOimport
dc.titleOptimization of scatterometry parameters for the gate level of the 90nm node
dc.typeProceedings paper
dc.contributor.imecauthorLeray, Philippe
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage1402
dc.source.endpage1412
dc.source.conferenceMetrology, Inspection, and Process Control for Microlithography XIX
dc.source.conferencedate27/02/2005
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 5752


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