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Optimisation of PECVD poly-SiGe layers for MEMS post-processing on top of CMOS

dc.contributor.authorMehta, Anshu
dc.contributor.authorGromova, Maria
dc.contributor.authorCzarnecki, Piotr
dc.contributor.authorBaert, Kris
dc.contributor.authorWitvrouw, Ann
dc.date.accessioned2021-10-16T03:22:31Z
dc.date.available2021-10-16T03:22:31Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10873
dc.sourceIIOimport
dc.titleOptimisation of PECVD poly-SiGe layers for MEMS post-processing on top of CMOS
dc.typeProceedings paper
dc.contributor.imecauthorCzarnecki, Piotr
dc.source.peerreviewyes
dc.source.beginpage1326
dc.source.endpage1329
dc.source.conferenceProceedings 13th International Conference on Solid State Sensors, Actuators and Microsystems - TRANSDUCERS
dc.source.conferencedate5/06/2005
dc.source.conferencelocationSeoul Korea
imec.availabilityPublished - imec


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