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Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

dc.contributor.authorMei, Bingfeng
dc.contributor.authorVeredas, Francisco-Javier
dc.contributor.authorMasschelein, Bart
dc.date.accessioned2021-10-16T03:23:32Z
dc.date.available2021-10-16T03:23:32Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10877
dc.sourceIIOimport
dc.titleMapping an H.264/AVC decoder onto the ADRES reconfigurable architecture
dc.typeProceedings paper
dc.contributor.imecauthorMasschelein, Bart
dc.contributor.orcidimecMasschelein, Bart::0000-0002-5636-1185
dc.source.peerreviewyes
dc.source.beginpage622
dc.source.endpage625
dc.source.conferenceProceedings International Conference on Field Programmable Logic and Applications - FPL
dc.source.conferencedate24/08/2005
dc.source.conferencelocationTampere Finland
imec.availabilityPublished - imec


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