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A system architecture case study for efficient calibration of memory organizations under process variability

dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorLobmaier, Florian
dc.contributor.authorStarzer, Florian
dc.contributor.authorMiranda Corbalan, Miguel
dc.contributor.authorHuemer, Mario
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-16T03:53:58Z
dc.date.available2021-10-16T03:53:58Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10981
dc.sourceIIOimport
dc.titleA system architecture case study for efficient calibration of memory organizations under process variability
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage42
dc.source.endpage49
dc.source.conferenceWorkshop on Application Specific Processors WASP
dc.source.conferencedate22/09/2005
dc.source.conferencelocationNew York, NY USA
imec.availabilityPublished - imec
imec.internalnotesin conjunction with IEEE/ACM Wsh. on hardware/software Co-design and intnl. system-level synthesis symposium (Codes-ISSS)


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