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32nm node technology development using interference immersion lithography

dc.contributor.authorSewell, H.
dc.contributor.authorMcCafferty, D.
dc.contributor.authorMarkoya, L.
dc.contributor.authorHendrickx, Eric
dc.contributor.authorHermans, Jan
dc.contributor.authorRonse, Kurt
dc.date.accessioned2021-10-16T04:58:41Z
dc.date.available2021-10-16T04:58:41Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11189
dc.sourceIIOimport
dc.title32nm node technology development using interference immersion lithography
dc.typeProceedings paper
dc.contributor.imecauthorHendrickx, Eric
dc.contributor.imecauthorHermans, Jan
dc.contributor.imecauthorRonse, Kurt
dc.contributor.orcidimecHermans, Jan::0000-0003-1249-8902
dc.contributor.orcidimecRonse, Kurt::0000-0003-0803-4267
dc.source.peerreviewno
dc.source.beginpage491
dc.source.endpage501
dc.source.conferenceAdvances in Resist Technology and Processing XXII
dc.source.conferencedate27/02/2005
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 5753


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