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Simulation methodology for analysis of substrate noise impact on analog / RF circuits including interconnect resistance

dc.contributor.authorSoens, Charlotte
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorWambacq, Piet
dc.contributor.authorDonnay, Stephane
dc.date.accessioned2021-10-16T05:18:53Z
dc.date.available2021-10-16T05:18:53Z
dc.date.issued2005-03
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11251
dc.sourceIIOimport
dc.titleSimulation methodology for analysis of substrate noise impact on analog / RF circuits including interconnect resistance
dc.typeProceedings paper
dc.contributor.imecauthorSoens, Charlotte
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorDonnay, Stephane
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecDonnay, Stephane::0000-0003-2489-4793
dc.source.peerreviewyes
dc.source.beginpage270
dc.source.endpage275
dc.source.conferenceProceedings of the Design, Automation and Test in Europe Conference and Exhibition - DATE
dc.source.conferencedate7/03/2005
dc.source.conferencelocationMünchen Germany
imec.availabilityPublished - imec


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