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Impact of recessed S/D SiGe integration parameters on device performance

dc.contributor.authorWashington, Lori
dc.contributor.authorNouri, Faran
dc.contributor.authorVerheyen, Peter
dc.contributor.authorMoroz, Victor
dc.contributor.authorKawaguchi, Marc
dc.contributor.authorYihwan, Kim
dc.contributor.authorSamoilov, Arkadiii
dc.contributor.authorJurczak, Gosia
dc.date.accessioned2021-10-16T07:03:58Z
dc.date.available2021-10-16T07:03:58Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11545
dc.sourceIIOimport
dc.titleImpact of recessed S/D SiGe integration parameters on device performance
dc.typeProceedings paper
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorJurczak, Gosia
dc.source.peerreviewno
dc.source.beginpage515
dc.source.endpage522
dc.source.conferenceAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment
dc.source.conferencedate15/05/2005
dc.source.conferencelocationQuebec Canada
imec.availabilityPublished - imec
imec.internalnotesElectrochemical Society Proceedings; Vol. 2005-05


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