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Method for endurance optimization of the HIMOStm flash memory cell in a 90nm CMOS technology

dc.contributor.authorYao, T.
dc.contributor.authorLowe, A.
dc.contributor.authorVermeulen, T.
dc.contributor.authorBellafiore, N.
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorWellekens, Dirk
dc.date.accessioned2021-10-16T07:21:55Z
dc.date.available2021-10-16T07:21:55Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11591
dc.sourceIIOimport
dc.titleMethod for endurance optimization of the HIMOStm flash memory cell in a 90nm CMOS technology
dc.typeProceedings paper
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.imecauthorWellekens, Dirk
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.source.peerreviewno
dc.source.beginpage662
dc.source.endpage663
dc.source.conference43rd Annual IEEE International Reliability Physics Symposium Proceedings
dc.source.conferencedate17/04/2005
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - imec


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