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Scalable gate-level models for power and timing analysis

dc.contributor.authorBadaroglu, Mustafa
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorWambacq, Piet
dc.contributor.authorDonnay, Stephane
dc.contributor.authorGielen, Georges
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-10-16T15:01:18Z
dc.date.available2021-10-16T15:01:18Z
dc.date.issued2007-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11668
dc.sourceIIOimport
dc.titleScalable gate-level models for power and timing analysis
dc.typeProceedings paper
dc.contributor.imecauthorBadaroglu, Mustafa
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorDonnay, Stephane
dc.contributor.imecauthorGielen, Georges
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecDonnay, Stephane::0000-0003-2489-4793
dc.source.peerreviewyes
dc.source.beginpage2938
dc.source.endpage2941
dc.source.conferenceIEEE International Symposium on Circuits and Systems - ISCAS
dc.source.conferencedate27/05/2007
dc.source.conferencelocationNew Orleans, LA USA
imec.availabilityPublished - imec


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