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Layout options for stability tuning of SRAM cells in multi-gate=FET technologies

dc.contributor.authorBauer, F.
dc.contributor.authorvon Arnim, Klaus
dc.contributor.authorPacha, C.
dc.contributor.authorSchultz, T.
dc.contributor.authorFulde, M.
dc.contributor.authorNackaerts, Axel
dc.contributor.authorJurczak, Gosia
dc.contributor.authorXiong, W.
dc.contributor.authorSan, K.T.
dc.contributor.authorCleavelin, C.R.
dc.contributor.authorSchrüfer, K.
dc.contributor.authorGeorgakos, G.
dc.contributor.authorSchmitt-Landsiedel, D.
dc.date.accessioned2021-10-16T15:03:00Z
dc.date.available2021-10-16T15:03:00Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11702
dc.sourceIIOimport
dc.titleLayout options for stability tuning of SRAM cells in multi-gate=FET technologies
dc.typeProceedings paper
dc.contributor.imecauthorJurczak, Gosia
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage392
dc.source.endpage395
dc.source.conferenceProceedings of the 33rd European Solid-State Circuits Conference - ESSCIRC
dc.source.conferencedate11/09/2007
dc.source.conferencelocationMünchen Germany
imec.availabilityPublished - imec


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