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A 65fJ/conversion-step, 0-to-50MS/s 0-to-0.7mW 9bit charge-sharing SAR ADC in 90nm digital CMOS

dc.contributor.authorCraninckx, Jan
dc.contributor.authorVan der Plas, Geert
dc.date.accessioned2021-10-16T15:25:51Z
dc.date.available2021-10-16T15:25:51Z
dc.date.issued2007-02
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11921
dc.sourceIIOimport
dc.titleA 65fJ/conversion-step, 0-to-50MS/s 0-to-0.7mW 9bit charge-sharing SAR ADC in 90nm digital CMOS
dc.typeProceedings paper
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.source.peerreviewno
dc.source.beginpage246
dc.source.endpage247
dc.source.conferenceInternational Solid-State Circuits Conference - ISSCC
dc.source.conferencedate11/02/2007
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - imec


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