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Double patterning design split implementation and validation for the 32nm node

dc.contributor.authorDrapeau, Martin
dc.contributor.authorWiaux, Vincent
dc.contributor.authorHendrickx, Eric
dc.contributor.authorVerhaegen, Staf
dc.contributor.authorMachida, Takahiro
dc.date.accessioned2021-10-16T15:55:56Z
dc.date.available2021-10-16T15:55:56Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12099
dc.sourceIIOimport
dc.titleDouble patterning design split implementation and validation for the 32nm node
dc.typeProceedings paper
dc.contributor.imecauthorWiaux, Vincent
dc.contributor.imecauthorHendrickx, Eric
dc.source.peerreviewno
dc.source.beginpage652109
dc.source.conferenceDesign for Manufacturability through Design-Process Integration
dc.source.conferencedate28/02/2007
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlwww.spie.org
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 6521


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